ICCCAS 2024 Invited Speaker

Haruo Kobayashi (SMIEEE)

Gunma University, Japan

Biography: Haruo Kobayashi received the B.S. and M.S. degrees in information physics from University of Tokyo in 1980 and 1982 respectively, the M.S. degree in electrical engineering from University of California, Los Angeles (UCLA) in 1989, and the Ph. D. degree in electrical engineering from Waseda University in 1995. He joined Yokogawa Electric Corp. Tokyo, Japan in 1982, and was engaged in research and development related to measuring instruments and mini-supercomputer. In 1997, he joined Gunma University as an Associate Professor and promoted to a Full Professor in Division of Electronics and Informatics. Currently he is Professor Emeritus there. His research interests include mixed-signal integrated circuit design & testing, and signal processing algorithms. He has published more than 160 journal papers and 450 international conference papers. Also, he has supervised 20 Ph. D. students and 160 M. S. students. He received the Yokoyama Award in Science and Technology in 2003. He is a Senior Member of IEEE, IEICE and IEEJ.
Speech Title: Recent Results of Authors’ Group: Extended Leslie-Singh Architecture of ΔΣ ADC and Mismatch Scrambling for High-Resolution Unary DAC with Virtual 3D Layout
Abstract: This talk introduces recent research results of author’s group in ADC/DAC areas. (i) The first one is an extended Leslie-Singh architecture of 1st-order ΔΣ AD modulator using an m-bit ADC and an n-bit DAC with 𝑚 ≥ 𝑛 ≥ 1 internally. SQNDR of the modulator for various (𝑚, 𝑛) is investigated by simulations and it was found that as m increases by 1, SQNDR improves by 6dB, while as n increases by 1, SQNDR improves by 3dB for 𝑚 ≫ 𝑛 but it saturates for 𝑚 ≈ 𝑛. We have clarified that as the DAC resolution increases by 1-bit, the SQNDR improves by 3dB since the input range for the modulator stable operation is extended. (iii) The second one is a unit cell mismatch scrambling method for high-resolution Nyquist-rate unary DAC based on virtual 3D layout (but actually 1D layout). This is to improve its spurious-free dynamic range (SFDR) with relatively simple interconnections and scrambling circuits.