ICCCAS 2024 Invited Speaker

Tetsuya Iizuka

University of Tokyo, Japan

Biography: Tetsuya Iizuka received the B.S., M.S., and Ph.D. degrees in electronic engineering from the University of Tokyo, Tokyo, Japan, in 2002, 2004, and 2007, respectively.
From 2007 to 2009, he was with THine Electronics Inc., Tokyo, Japan, as a high-speed serial interface circuit engineer. He joined the University of Tokyo in 2009, where he is currently an Associate Professor with Systems Design Lab., School of Engineering. From 2013 to 2015, he was a Visiting Scholar with the University of California, Los Angeles, CA, USA. His current research interests include data conversion and frequency synthesis techniques, high-speed analog integrated circuits, digitally-assisted analog circuits and VLSI computer-aided design.
Dr. Iizuka is a member of the Institute of Electrical and Electronics Engineers (IEEE) and the Institute of Electronics, Information and Communication Engineers (IEICE). He was a member of the IEEE International Solid-State Circuits Conference (ISSCC) Technical Program Committee from 2013 to 2017 and a member of the IEEE Custom Integrated Circuits Conference (CICC) Technical Program Committee from 2014 to 2019. From 2016 to 2018, he served as the Editor of IEICE Electronics Express (ELEX). He is currently serving as a member of the IEEE Asian Solid-State Circuits Conference (A-SSCC) and IEEE VLSI Symposium on Circuits Technical Program Committees.
He is a recipient of the 21st Marubun Research Encouragement Commendation from Marubun Research Promotion Foundation in 2018, the 13th Wakashachi Encouragement Award First Prize in 2019 and the 18th Funai Academic Prize from Funai Foundation for Information Technology in 2019. He is a co-recipient of the IEEE International Test Conference Ned Kornfield Best Paper Award in 2016.
Speech Title: An Analysis-based Systematic Design of CMOS SAR A/D Converters
Abstract: This presentation introduces a systematic design framework for ADC optimization. Our emphasis is on a robust design that is highly repeatable, which is driven by a deep understanding of the behavior of circuit building blocks. A 10 b 500 MS/s single-channel SAR ADC designed in this framework displays uniform performance for inputs up to 2GHz at state-of-the-art FoM, which demonstrates the power of design based on analytical expressions.