ICCCAS 2024 Invited Speaker

Yasuhiro Takahashi

Gifu University, Japan

Biography: Yasuhiro TAKAHASHI was born in Yamagata, Japan, in July, 1977. He received a B.E., M.E., and Ph.D. in electronic engineering from Yamagata University, Japan in 2000, 2002, and 2005, respectively. He was a research associate at the Department of Electrical and Electronic Engineering, Faculty of Engineering, Gifu University, from April 2005 to March 2007. He was an assistant professor there from April 2007 to November 2014 and is currently an associate professor.
His research interests include low-power VLSI design, with a particular emphasis on analog/digital circuits, CAD techniques for implementing high-performance DSP functions, and a new approach to nonlinear circuits design using memristors. He has published 150+ papers in refereed journals and conference papers in these and related areas.
He received an IEICE 2017 system and signal processing subsociety achievement award, IEEE IMPACT-EMAP 2014 best poster award, a 9th LSI IP design award in 2007, and also received a 2002 master's degree thesis award of the Graduate School of Science and Engineering, Yamagata University.
He holds 13 (One U.S., 11 Japan, and One China) patents regarding low-power circuit design using adiabatic switching principle. He is a member of IEEE, IEEJ, and IEICE.
Speech Title: A 0.06 mm2, 0.9 pJ/bit, 25 Gb/s Optical Receiver Front-end Module in 65 nm CMOS
Abstract: This paper presents the measurement results of a 0.9 pJ/bit, 25-Gb/s optical receiver front-end based on the active-voltage current-feedback (AVCF) transimpedance amplifier (TIA). The propose TIA core circuit has the stable operation and the increased gain compared with the conventional TIAs. The occupied chip area with I/O and DC pads is 660 um x 580 um (= 0.38 mm2) and the proposed analog front-end TIA occupies only 360 um x 160 um (approximately 0.06 mm2). The proposed module operates at 25-Gb/s with a supply voltage of 1.0 V and consumes only 22.6 mW.