ICCCAS Invited Speaker

Hiroyuki Yotsuyanagi

Tokushima University, Japan

Biography: Hiroyuki Yotsuyanagi received the B.E., M.E. and Ph.D degrees from Osaka University, in 1993, 1995 and 1998, respectively. He is currently a Professor of Division of Science and Technology, Graduate School of Technology, Industrial and Social Sciences, Tokushima University. His research interests include design-for-testability methods for delay testing and post-bond testing of 3D ICs. He is a member of Institute of Electronics, Information and Communication Engineers of Japan (IEICE) and the Japan Institute of Electronics Packaging (JIEP), and a senior member of the Institute of Electrical and Electronics Engineers (IEEE).
Speech Title: A delay testable boundary scan with an embedded time-to-digital converter for testing chip interconnects
Abstract: With the growing demand for implementing IC chips within packages, such as 3D stacks and 2.5D integration, testing interconnects between ICs has become increasingly important. In this talk, we introduce a test structure designed to detect delay faults in interconnects. The proposed design is based on boundary scan and incorporates a time-to-digital converter. We will also present the experimental results obtained from our fabricated chips.