ICCCAS Invited Speaker
Hitoshi Aoki (SMIEEE)
Rohm Semiconductor, Japan
Biography: Dr.
Hitoshi Aoki is a technical adviser at Rohm Co. Itd.
Previously, he was a full time professor at Teikyo Heisei University and
visiting professor at Gunma University in Japan. He has over 35 years of
device modeling experience in electronic industries. Prior to his carrier
with Universities, Dr. Aoki founded a modeling company, MoDeCH Inc. in 2002,
where he is now an Executive Advisor. He had been working at some leading
companies of electronics in both the U.S.A. and Japan including the ULSI
Research Laboratory of Hewlett-Packard Laboratories U.S.A, Agilent
Technology, and Hewlett-Packard Japan. He received the Ph.D. degree from the
Tokyo Institute of Technology, Tokyo, Japan, in 2002. He authored and
coauthored two books related to compact modeling and more than 130 technical
papers. Dr. Aoki is a senior member of IEEE.
Speech Title: Frequency Dispersion Modeling based on
Trapping Effect in AlGaN/GaN HEMTs
Abstract:
GaN-channel heterostructure field-effect transistors (HFETs) have
been extensively studied over the past two decades. This interest has been
due to the excellent properties of the IIInitride material system, such as
high electron saturation velocity, large critical electric field, and large
polar 2-D electron gas (2DEG) concentration.
Frequency dispersion of the output conductance attributed to trapping
phenomena. The frequency dispersion of the output conductance or
transconductance was largely investigated in GaAs MESFET and III-V HEMTs
during the past. It was also observed in AlGaN/GaN HEMTs and may be
attributed to traps located in the GaN channel layer, at the AlGaN/GaN
interface or at the surface area. Trapping of carriers are generally
responsible of parasitic effects, such as the virtual second gate, which
directly impacts the power amplifier characteristics, the noise properties,
and the reliability of the devices.
In this research, frequency dispersion of transconductance and output
conductance in AlGaN/GaN high electron mobility transistors is modeled. The
model includes two voltage controlled current sources and a small-signal
equivalent circuit. Trapping effects are taken into account with parasitic
electrical networks including distributed time constants. The model has been
verified with S-parameter measurements.