ICCCAS Invited Speaker

Shi-Yu Huang (SMIEEE)

National Tsing Hua University

Biography: Shi-Yu Huang received his B.S. and M.S. degrees in Electrical Engineering from National Taiwan University in 1988, and 1992, and a Ph.D. degree in Electrical and Computer Engineering from the University of California, Santa Barbara in 1997, respectively. He has been on the faculty of the EE Dept., National Tsing Hua University, Taiwan, since 1999. His research interests include VLSI design, automation, and testing, with a current emphasis on All-Digital Phase-Locked Loop (ADPLL) design and Time-to-Digital Converter (TDC) design and their applications in parametric fault testing and monitoring in 3D ICs. He ever served as Program Co-Chair or General Chairs or Co-Chairs in several IEEE Conferences/symposia/workshops (2004, 2009 ATS, 2005, 2006 MTDT, 2014, 2015 VLSI-DAT, and 2017 ITC-Asia). He ever served as an Associate Editor for IEEE Trans. on Computers from 2015 to 2018, and is now an Associate Editor for IEEE Trans. On Emerging Topics in Computing.
Speech Title: Calibration of a Time-to-Digital Converter for Accurate Jitter Measurement
Abstract: A Time-to-Digital Converter can measure the clock period jitter of a clock signal generated by an on-chip Phase-Locked Loop (PLL) circuit. However, due to process variation, the timing resolution may not be very stable, and which will introduce measurement error. In this talk, we elaborate on a calibration scheme to overcome this issue. We treat the TDC and the PLL as a combo-circuit. In the calibration phase, the PLL is used to generate training clock signal of various clock frequencies to rectify the resolution of the TDC. In the measurement phase, the rectified TDC can then be used to measure the clock period jitter of PLL. Overall, we found that the worst-case resolution of a TDC can be reduced from 5.1ps to 3.8ps, and the error of the measurement can be reduced from 7.03ps to 1.28ps.